Optimal design on asynchronous system with gate-level pipelining

摘要

Automatic optimal design of asynchronous system based on gate-level handshake pipelined control is proposed. Gate-level alignment, fan-out and loop optimization are important to maintain throughput of the system. With netlist generated from RTL by a commercially available logic synthesize tool, our method optimizes insertion of buffers to optimally align among gates. Benchmark results show the proposed method realizes about 1.3× higher throughput than synchronous circuit in 65nm process, with area increase of 15×.