The Network Performance Analysis Platform and Its Application to Network Buffer Evaluation of the Embedded System

摘要

In this work, a network simulator is developed to predict the amount of hardware resources required for an embedded large-scale data processing system. It is difficult to simulate with the existing hardware simulator because the calculation time of processors lasts several days. This large time-consumption is caused by the fact that the processor module is made up of many components like CPU cores and shared buses. The target of this work is to complete the transmission simulation with one million packets in six hours. To reduce the analysis time, we focused on the shared bus of the processor and found that it is possible to estimate the amount of network buffer usage in a congestion state of packets in the shared bus. We have developed a shared bus timing model for calculating the packet transmission capacity by using the parameters related to the CPU core bus access time of the processor. Thereby, its simulation throughput can be increased up to 13 thousand packets per minute. The simulation results show that one million packets could be completed in two and a half hours by using the proposed techniques and confirmed that the proposed simulator can be used to optimize a large-scale data processing system.