SyMPLES-CVL: A SysML and CVL Based Approach for Product-Line Development of Embedded Systems

摘要

Background: A Software Product Line (SPL) is a group of systems that share a common set of features satisfying the specific needs of a market segment. These systems are systematicaly developed from a common set of core assets. Objective: This paper proposes SyMPLES-CVL, an alternative approach to the management of variability based on SysML models to support the development of SPLs for embedded systems. In addition, we present a comparative study between our previous approach, SyMPLES-SMarty, and SyMPLES-CVL. Method: SyMPLES-CVL was specified based on SyMPLES-SMarty, then an experimental study was carry to compare the approaches. A total of 20 participants with Software Engineering background were divided into two groups, one for each approach. The data were collected with the support of questionnaires which was analysed based on test hypotheses using inferential statistics. Results: SyMPLES-CVL was not considered significantly more effective than SyMPLES-SMarty at an significance level of 0.05 for T-Test test. Limitations: Generalization of results is limited due to the sample size of this study. Conclusion: The results showed that the approaches compared did not have a significant difference in terms of effectiveness, although they use different means (annotative and compositional) for the management of variability in SPLs. Paper Category: Experimental and Technological.