Design and simulation of hafnium dioxide based charge trapping flash memory device

摘要

The demand of lower power and smaller dimension of flash memory requires size down scaling of the device. To meet this requirements, charge trapping flash using high-k dielectric is considered as one of the future technologies. In this paper, the design and simulation of HfO2 based charge trapping flash (CTF) is investigated. The CTF is based on a typical 160 nm NMOS structure with hafnium dioxide layer and ONO embedded in the gate stack. The program and erase (P/E) states of the device are simulated for several cycles to achieve stead-state charge density in trapping layer. Current-voltage characteristics are also run to extract threshold voltages of the P/E states. The threshold voltage shift is 0.82 V. A 10-year simulation is also taken to characterize the long-term charge retention capabilities of the structure. The device shows improved barrier tunnelling current and high retention ability for electron as well as their high density.