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Parametric Degradation in Transistors

机译:晶体管中的参数劣化

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Understanding degradation of key transistor parameters is essential in addressing transistor reliability issues. What are some of the key aging kinetics that causes transistor degradation? Understanding device reliability issues through physics-of-failure analysis provides insights that often are unobtainable from experimental work alone. The more one is able to understand, the higher is the likelihood that improvements can be made in device design and in testing methods. Parametric degradation in transistors is described to help explain overall reliability, relationships to device junction aging, and to aid in predicting parameter drift. This work gives a number simple formulations that help provide insight into why key device transistor parameters age. This is provided in both the bipolar and FET (Field-Effect Transistor) case. Although the formulations are simple, they illustrate the important role that leakage current plays in aging of key device parameters for bipolar and FET transistors. Aging of key transistor device parameter for the Bipolar and FET case have been described. Leakage have been expressed as leaky capacitors and relationships established to aging. In the bipolar case for the common-emitter configuration, we find that transistor beta aging is directly proportional to the fractional change in the base-emitter leakage current. In the FET case, transconductance aging results from a change in the drain-source resistance and gate leakage. This modeling also helps explain their observed log(time) degradation of these parameters observed on life test. We presented simple formulations to help understand this degradation that links this aging to junction temperature dependent leakage current mechanisms. We presented life test data that is representative of typical aging on both HBTs and MESFETs. Additionally, we used a TAT model to link these results with experimentally observed log(time) degradation. Such formulations are important in the understanding of transistor reliability.
机译:了解关键晶体管参数的劣化在寻址晶体管可靠性问题方面是必不可少的。什么是导致晶体管退化的关键老化动力学是什么?了解通过物理学分析的设备可靠性问题提供了常见于实验工作的洞察力。能够理解的越多,可以在设备设计和测试方法中提高改进的可能性越高。描述了晶体管中的参数劣化,以帮助解释整体可靠性,与设备结老化的关系,并有助于预测参数漂移。这项工作提供了一个数字简单配方,有助于深入了解键设备晶体管参数年龄。这是在双极和FET(场效应晶体管)壳体中提供的。虽然配方很简单,但它们说明了泄漏电流在双极和FET晶体管的关键装置参数方面发挥的重要作用。已经描述了双极和FET壳体的关键晶体管器件参数的老化。泄漏已表示为泄漏的电容器和建立老化的关系。在共用发射极配置的双极性壳中,我们发现晶体管β老化与基极发射极漏电流的分数变化成正比。在FET壳体中,跨导老化由漏极源电阻和栅极泄漏的变化产生。该建模还有助于解释其观察到的日志(时间)在生命测试上观察到这些参数的劣化。我们提出了简单的配方,以帮助了解这种降级,将这种老化与结温依赖性漏电流机构联系起来。我们提出了在HBT和MESFET上代表典型老化的生命测试数据。此外,我们使用TAT模型将这些结果与实验观察到的日志(TIME)劣化链接。这种配方在理解晶体管可靠性方面是重要的。

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