Threshold voltage shift due to incidental pulse on non-stressed pins during HBM testing

摘要

An unexpected voltage pulse in ESD HBM tester's non-stress channels led to phase shift error failure in a sensitive phase comparator circuit. The failure occurred due to threshold voltage shift of the input PMOS transistor. This unwarranted stress was shown to come from relay capacitance and distributed resistance of relay-based HBM tester.