System-level ESD failure diagnosis with chip-package-system dynamic ESD simulation

摘要

A comprehensive chip-package-system (CPS) electrostatic discharge (ESD) simulation methodology is developed for addressing IEC61000-4-2 testing conditions. An innovative chip ESD compact model is proposed, combined with full-wave models of the ESD gun, ESD protection devices, PCB wires/vias and connectors for CPS analysis. Two examples of CPS ESD application are illustrated demonstrating good correlation with measurement.