3D Integration: New opportunities in defense against cache-timing side-channel attacks

摘要

Recently, following the work pioneered by Kocher [1], using cache behavior as a timing side-channel to leak critical system information has received lots of attentions because of its easy-to-implement nature and amazingly good results. Recent attacks have been demonstrated to successfully leak the full key from many commonly used encryption algorithms including RSA, AES, etc. These attacks pose great threats to applications that depend on these encryption methods such as banking systems, military systems, etc. To mitigate the increasing threat, numerous countermeasures, mostly software patches, have been proposed. Hardware mitigations, however, have been less pursued. In this paper, we show that emerging 3D integration technology offers new opportunities in defense against these attacks. We propose two cache design mechanisms that can make the attacker's job harder, even impossible. Experimental results show that using our cache design, the side-channel leakage is significantly reduced while still achieving performance gains over a conventional 2D system.