Innovative practices session 7C: Reduced pin-count testing — How low can we go?

摘要

Multi-site testing is generally regarded as the most-effective way to reduce the cost of test. Testing two devices on an ATE at the same time is half the cost of testing only one, but only if the ATE does not need twice as many channels. It is general practice in industry to use reduced pin-count test (RPCT) access to facilitate testing more ICs in parallel, as well as testing high pin-count ICs on low channel-count testers. This session will address how quality is maintained for the I/Os that are not accessed by ATE channels, advantages of RPCT beyond cost reduction, disadvantages of RPCT, yield impact, differences between RPCT for wafer-sort and final test, DFT for RPCT, handling mixed-signal functions, and ultimately, the smallest number of signal pins that can be accessed for thoroughly testing an IC.