This paper proposes a new method that uses normal production mask set in combination with stepper alignment control feature to generate a wide range of alignment offsets with a possible die to die misalignment increment of 10 nm. Experimental results with the new method are reported in this paper. Once the true overlay error budget is known, an adequate sampling and a precise accounting method are required to report the alignment performance. It is found that current accounting method could report an overlay error that is 100% larger than the worst misalignment sampled. A new method to partition the overlay data into subgroups was proposed to take advantage of the nature of the stepper alignment and product overlay error sources. It truly reflects the misalignment from wafer to wafer and takes into account the worst case, which is what the chip designers really care about.
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