A Simple Double Mapping Based SVPWM Method for Balancing DC-Link Capacitor Voltages of Five-Level Diode-Clamped Converters

摘要

DC capacitor voltage imbalances are one of the major technical concerns for higher level diode-clamped converters (DCC). In this paper, a simple double mapping based space vector pulse width modulation (SVPWM) algorithm is proposed for balancing dc-link capacitor voltages of five-level DCC utilizing the switching redundancies. By choosing the appropriate switching pattern and its duration simultaneously, the voltage across each capacitor can be controlled adaptively. The developed mapping approach considers minimum loss SVPWM to address capacitor voltage equalization at high modulation indices. After having all the obtainable switching combinations, the flve-levelDCC can be mapped into any lower level DCC structure depending on capacitor voltages to increase available switching redundancy. The duty cycles are calculated by taking into account only two-level SVPWM and can be updated for any higher level converter structure by adding required level number. In the proposed scheme dc-capacitor voltage balancing is attained with minimal switching operation, without any requirement of additional auxiliary power circuits. The simulation results validate the capability of mapping based SVPWM strategy to regulate the dc-link capacitor voltages for five-level DCC at different operating conditions.