首页> 外文会议>Annual IEEE Applied Power Electronics Conference and Exposition >Harmonic filter topologies for low DC bus capacitance of 6-pulse rectifier front end adjustable speed drives
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Harmonic filter topologies for low DC bus capacitance of 6-pulse rectifier front end adjustable speed drives

机译:6脉冲整流器前端可调速度驱动器的低直流总线电容的谐波滤波器拓扑

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Passive harmonic filter topologies that mitigate harmonic problems in three-phase power system due to low DC bus capacitance of 6-pulse rectifier front end adjustable speed drives are proposed. The first filter topology is the modified typical LLCL harmonic filter with a capacitor added across the input and output reactors of each phase. The second filter topology is also LLCL harmonic filter with a capacitor and damping resistor added in series across the input and output reactors of each phase. Both topologies create high order filters. The filter transfer functions are derived. A prototype was constructed and tested with the results presented. Simulation results correlated well with the prototype test data. The prototype filter for both topologies reduced the total harmonic current distortion (THID) below 5% to meet the limits of IEEE 519.
机译:提出了由于6脉冲整流器前端可调速度驱动器的低直流总线电容而减轻三相电力系统中的谐波问题的被动谐波滤波器拓扑。第一滤波器拓扑是修改的典型LLCL谐波滤波器,其中电容器跨越每个阶段的输入和输出反应器。第二滤波器拓扑也是LLCL谐波滤波器,其中电容器和阻尼电阻串联添加在每个相的输入和输出电抗器上。这两个拓扑都会创建高阶滤波器。派生滤波器传输函数。用呈现的结果构建并测试了原型。仿真结果与原型测试数据相相关。两个拓扑的原型滤波器降低了低于5 %的总谐波电流失真(Thid)以满足IEEE 519的限制。

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