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Wide-range 16-phases DLL based on improved dead-zone phase detector and reduced gain charge pump

机译:基于改进的死区相位检测器和降低的增益电荷泵的宽范围16相DLL

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In this paper, a low jitter 16-phases DLL is proposed based on a simple and sensitive phase detector. Dead-Zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched differential pairs. Duty cycle of output differential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80MHZ to 410MHz, consuming total power of 3.5mW and 5.6mW, respectively. The dead-zone of PD is also reduced from 80ps to 14ps when the pulse generator section is eliminated. Also, RMS jitter of about 45ps and 1.76ps are obtained at 80MHz and 410MHz, respectively, when the supply voltage is subject to around 50mvolts peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05mm active area in a 0.18μm CMOS technology.
机译:本文提出了一种基于简单且灵敏的相位检测器的低抖动16相DLL。与常规结构相比,提出的PD的死区得到了改善,在常规结构中,脉冲发生器会延迟PD响应并降低灵敏度。同样,对电荷泵的传统结构进行了修改,以便在PD的连续输出中注入少量电荷。通过减去故意不匹配的差分对的尾电流,可在电荷泵中提供较小的偏置电流。使用延迟元件上的共模设置策略,可将输出差分相位的占空比调整为50%左右。仿真结果表明,DLL环路可以在80MHZ至410MHz的频率范围内提供16个相位,分别消耗3.5mW和5.6mW的总功率。当消除脉冲发生器部分时,PD的死区也从80ps减小到14ps。同样,当电源电压受到约50mV峰峰值噪声干扰时,分别在80MHz和410MHz时分别获得约45ps和1.76ps的RMS抖动。所提出的DLL可以在0.18μmCMOS技术中小于0.05mm的有源区域中实现。

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