An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction

摘要

This paper presents an area efficient 3-tap speculative Decision Feedback Equalizer (DFE) with a novel current-integrating summer for data self correction in standard CMOS 180nm technology node. The conventional first-tap speculative half-rate DFE is composed of four different paths, which have exactly same hardware. In this paper, a novel area efficient DFE is proposed where the four summers are reduced to two. By using switched-capacitors to separate the first speculative tap, two parallel paths for speculation can be driven by a single summer. The proposed DFE consumes 17.4 mW with 1.8V supply when equalizing 4Gb/s data passed over a channel with 28 dB loss at 2GHz.