A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs

摘要

This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNR_jitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 μm ×360 μ m silicon area, is realized in a SiGe BiCMOS 0.13 μ m process.