High Throughput Architecture for OCTAGON Network on Chip

摘要

High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 17% while preserving the average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared to the total metal resources required to implement OCTAGON design. The extra power consumption required to achieve the proposed architecture is 2% of the total power consumption of the OCTAGON architecture.