Digitisation of signals at RF imposes severe noise and linearity constraints. Furthermore, the drive towards integration with deep submicron CMOS process aggravates the difficulties in high frequency mixed signal circuit design. This paper first summarises the challenges in system and circuit facing GHz IF complex sampling. It then proposes a charge sampling receiver architecture which combines MEMS filter and complex FIR sampling filter in order to achieve high IF digitization suitable for multi-standard cellular applications. The architecture is validated through system behavioural models emulating deep submicron MOS characteristics. It can be shown mat with existing MEMS filter technology and advanced standard CMOS process, it is possible to realise a reconfigurable high IF SDR receiver. A circuit version of integrated MEMS filter and sampling filter in CMOS is in the works to validate the proposed system.
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