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Effects of structured parallelism by parallel design patterns on embedded hard real-time systems

机译:并行设计模式对结构化并行性的影响对嵌入式硬实时系统的影响

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Parallel multi-threaded applications are needed to gain advantage from multi- and many-core processors. Such processors are more frequently considered for embedded hard real-time with defined timing guarantees, too. The static timing analysis, which is one way to calculate the worst-case execution time (WCET) of parallel applications, is complex and time-consuming due to the difficulty to analyze the interferences of threads and the high annotation effort to resolve it.
机译:需要并行多线程应用程序才能从多核和多核处理器中获得优势。此类处理器也更经常用于具有定义的时序保证的嵌入式硬实时技术。静态时序分析是计算并行应用程序的最坏情况执行时间(WCET)的一种方法,由于难以分析线程的干扰以及解决该问题的大量注释工作,因此非常复杂且耗时。

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