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Output-bit selection with X-avoidance using multiple counters for test-response compaction

机译:使用多个计数器的X避免输出位选择,以进行测试响应压缩

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Output-bit selection is a recently proposed test-response compaction approach that can effectively deal with aliasing, unknown-value, and low-diagnosis problems. This approach has been implemented using a single counter and a multiplexer without considering unknown values. Also, such an implementation may require the application of a pattern multiple times in order to observe all selected responses. In this paper, we present a multiple-counter-based architecture with a new selection algorithm that can avoid most unknown-values yet achieve high compaction ratio. The remaining small number of unknowns can then be dealt with using some simple masking logic. Experiments on IWLS'05 circuits show that even with 16% unknown responses, all unknown values can be handled with 88.92%~93.21% response-volume reduction still achieved and only a moderate increase in test-application time.
机译:输出位选择是最近提出的测试响应压缩方法,可以有效处理混叠,未知值和低诊断性问题。已经使用单个计数器和多路复用器实现了该方法,而无需考虑未知值。同样,这样的实现可能需要多次应用模式以观察所有选择的响应。在本文中,我们提出了一种基于多计数器的体系结构,该体系结构具有一种新的选择算法,该算法可以避免大多数未知值,但可以实现较高的压缩率。然后可以使用一些简单的掩蔽逻辑来处理剩余的少量未知数。在IWLS'05电路上进行的实验表明,即使有16%的未知响应,仍可以处理88.92%〜93.21%的响应量,但仍可以处理所有未知值,并且仅适度增加测试应用时间。

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