Fully delay testable sequential circuits and problem of their structural minimization

摘要

The method of a sequential circuit design based on using a mixed description of a circuit behavior is considered. A combinational part of a sequential circuit is examined. Its behavior is represented with a composition of ROBDD-graphs and monotonous products. The method provides fully delay testability of a combinational part of a sequential circuit. It is oriented to cut down the path lengths of the obtained circuits. Experimental results are given that demonstrate advantages of the method. The possibilities of further structural minimization of the circuits are discussed.