High-speed, Low Switching Noise and Load Adaptive Output Buffer

摘要

A new output buffer with low switching noise and load adaptability is designed based on a TSMC 90nm CMOS technology. The proposed buffer can reduce switching noise induced on supply lines and output ringing while achieving very fast output transitions. Moreover, the load adaptive method is simple and effective. Simulation results demonstrate that the proposed buffer achieves 4.1%-53.5% improvements in ground bounce and 2.9%- 15.2% reductions in output ringing compared with those of the AC/DC buffer. Meanwhile, it reduces ground bounce by 6.5%- 17.6% and output ringing by 3.8%- 10.9% relative to the CSR buffer.