Design challenges of high speed ADC in CMOS technology for next generation optical communication applications

摘要

The next generation commercial optical communication requires ADCs with more than 50GS/s and at least 5 ENOB. For this ultra-high speed requirement, the time-interleaved architecture is the best choice among various types of ADCs. This paper first examines the key challenges of these high-speed time-interleaved ADCs from the perspective of designers. Then detailed design considerations are presented, including time-interleaved architecture, sub-ADC and the analysis of channel mismatch effects. Finally, digitally calibration designs are briefly introduced.