Design of The Delta-Sigma Digital-to-Analog Converter For High-Resolution Micro-Nano Satellite Applications

摘要

The presented 24-bit 6.4MHz sample-rate digital-to-analog converter (DAC) achieves above 130dB dynamic range in the 25 KHz band, and consumes 26.5mW with a 5-V power supply for Micro-Nano satellite systems. The digital part of the DAC includes digital interpolation filter, multi-bit MASH2-1 sigma-delta modulator, and Incremental Data Weight Average (IDWA) algorithm. The analog part of the DAC is the low-noise switched-capacitor (SC) reconstruction filter which contains only one opamp. The 128 times up-sampling hardware-efficient multistage interpolation filter based on the desensitized half-band filter's structure attains above 100dB out of band attenuation while the passband ripple is less than 0.001dB. The whole chip area is about 2.43mm^{2 in a 0.35µm 4-metal CMOS process. The post mixed-signal layout simulation shows that the Effective Number Of Bits (ENOB) is 22bits.}