annealing; power MOSFET; semiconductor junctions; sputter etching; DRI etching; annealing; area specific ON resistance; breakdown voltage; crystal defects; deep reactive ion etching; design complexity; device fabrication; frequency 1.027 GHz; maximum operating switching frequency; optimized process design flow; process device; process simulation; silicon CB SJ VDMOS; silicon charge balance superjunction vertical double-diffused MOS; superjunction VDMOS fabrication; temperature 1100 degC; temperature 1150 degC; trench p-pillar; voltage 590 V; Doping; Fabrication; Junctions; Logic gates; MOSFET; Silicon; CB; RDSonA BV; RESURF; SJ; crystal defect;
机译:<![CDATA [优化纳米等离子银的制造氮掺杂氧化锌(AG
机译:<![CDATA [FATHRATION Z-Scheme GC
机译:<![CDATA [制作双壳FE
机译:设计理论和制造工艺集成32nm节点Si,Ge和Si
机译:用于汽车应用的60V VDMOS设计和制造
机译:当用于分化PLB-985细胞时INF-γ通过上调phox蛋白增强Nox2活性但自身不诱导Nox2活性
机译:Bi