A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications

摘要

Electrostatic discharge (ESD) and Electrical Overstress (EOS) are well-known problems in integrated circuits that affect the reliability, yield and cost. In addition, it has been reported that ESD/EOS contributes to significantly large fraction of failures [1]. It is important to design ESD protection circuits that are able to prevent these failures. In this work, a 65 nm hybrid ESD power supply clamp, which consists of static and transient clamps, for low leakage applications is presented. A diode configuration is used as a static clamp, while the transient clamp consists of a PMOS as the main transistor with body bias and thyristor as a delay element. Simulation and measurement results show that the clamp has fast response for ESD-like event. Extensive stability analysis demonstrates that the clamp is stable against false triggering, oscillation, power supply noise and latch-up. Carried out measurement results also show that the clamp is capable of handling 1.55A of current while its leakage is only 32.9nA, whereas the traditional clamp has a leakage of 1.47μA.