A reconfigurable buck-boost switched capacitor converter architecture for multiple, distributed on-chip load applications

摘要

This paper presents the design of a dual-output reconfigurable buck-boost switched capacitor converter architecture that can be adapted for applications requiring multiple, distributed on-chip loads. This system uses adaptive gain control and discrete frequency scaling to regulate power delivered. Core-interleaving and an enhanced load regulation scheme have also been adopted to improve performance. The converter provides a fully-integrated, low-area and fully digital solution. Design and implementation using a standard bulk CMOS 0.18μm process provide simulation results showing that the converter has an output voltage range of 1.0–2.2V, can deliver up to 5mA in load current and is up to 67% efficient.