This paper presents the Parallel Heterogeneous Architecture Technology (PHAT), a scalable design methodology for prototyping and evaluating heterogeneous arrays of software-programmable VLIW processors and both manually designed and automatically-compiled custom hardware accelerators, using a shared memory architecture for communication. We discuss the trade-offs and breakeven point for switching from bus-based to network-on-chip interconnects, the interface and protocols for connecting distributed on-chip caches and multi-bank out-of-order off-chip-memories, as well as the impact of floorplanning on the quality of results for implementation on Xilinx Virtex 6 LX 760 devices. The capabilities are evaluated at the system-level on the multi-FPGA Convey HC-1ex hybrid-core computer, accessing its high-performance memory system, and integrating r-VEX processor cores with IP blocks for SHA and FFT computations.
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