The virtual channel flow control approach provides an efficient way for the high throughput of the on-chip routers. However, allocating the virtual channels (VCs) statically results in a waste of the area and energy consumption. To remedy this drawback, we propose a novel dynamic virtual channel architecture (DVCA) in this paper. By inspecting the physical link state and speculating the packet transferring, it dispenses a variable number of VCs to escape the head-of-line (HOL) blockings to maximize the throughput, and avoids the useless VC allocations to reduce the packet latencies. In its implementation, the VC allocation unit, the switch allocation unit as well as the VC control unit are modified to complete the DVCA router design. Then, under the 90nm CMOS process, the proposed routers using 50% buffers provide 6.2% throughput increase and 4.1% latency decrease averagely with the savings of 30.9% area and 31.3% power consumption compared to traditional routers.
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