Hierarchical Synchronization between Processes in a High-Performance Execution Support of Dataflow Process Networks on Many-Core Architectures

摘要

When using vector clocks to synchronize processes in a computation, the problem of the vector clock dimension is well known and an acknowledged difficulty. In dataflow process networks, a compiler can rely on some process properties to create a hierarchical view of inter-process synchronization, achieving bounded vector clock dimension. In this paper, we present two approaches to reduce the vector clock dimensions, these approaches can be clearly combination between them. The first one is mainly based on run length encoding heuristic, the second one is achieved by means of 0/1 integer programming model with modeling into the graph partitioning problem.