Multiplierless FIR filter design using Global Valued Numbering and architecture

摘要

Here the optimized gate level area problem in digit serial MCM designs, and design architectures is being introduced. Digit serial design offers less complexity MCM operation by increasing the delay of operation. Several efficient and accurate algorithms have been introduced to design lower complexity bit-parallel multiplication operation for multiple constant multiplication. In this project, direct form, transposed form as well as proposed MCM has been implemented. Using MCM technique, area and power is reduced in compromise with delay constraint. In order to reduce delay even more we can use Global Valued Numbering (GVN). Using variable assignment method, reduced delay as well as better area and power minimization can be obtained.