Flag and Register Array Based High Performance Instruction Set Architecture of Embedded Processor

摘要

Here, assumption is that if we add 8 numbers from register array then it takes 120ns when execution time is 5ns and register access time is 10ns. If we add same 8 number using one by one fetching from memory then it takes 840ns to add 8 numbers. In that way we are saving 720ns, i.e., 85.7% time saving in execution of add instruction to add 8 numbers. In this way, our Instruction Set based on Flag and Register Array provides high performance. And in this paper comparison of this instruction set with existing instruction set of advanced processor architecture like PIC16FXX, AVR ATMEGA8, 8051.