Parallel ASIP Based Design of Turbo Decoder

摘要

Application Specific Instruction-set Processor (ASIP) has a general-purpose architecture that can be modified and used in a variety of applications. However, this increases the power and memory utilization and affects the functionality and efficiency of ASIP. This paper is defining the flexibility of ASIP for Turbo decoding in term of its functionality and architecture for specific applications such as DVB-RCS, 3GPP. The proposed architecture has a dedicated SIMD (Single Instruction Set Multiple Data), coupled with distributed memory based ASIP. It has been concluded in this paper that ASIP facilitates parallelism at different levels, thereby, increasing the efficiency, power consumption, and processing time.