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ADVANCES IN FEFLO

机译:FEFLO的进展

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摘要

This paper summarizes the major improvements and developments that have taken place during the last year for FEFLO, a general-purpose CFD code based on adaptive, unstructured grids. All aspects of a comprehensive simulation pipeline: pre-processing, gridding, field solvers and post-processing saw important advances, and are treated. The advent of machines with millions of cores focused a lot of the developments on distributed memory aspects of field solvers and multiphysics modules. Parallel grid generation, particles and flow, parallel interpolation, parallel domain splitting and repartitioning for multiphysics were all considered. Furthermore, timings on Xeon and AMD chips led to the realization that memory transfers play a considerable role as compared to floating point operations, something previous chip generations did not exhibit. This led to a thorough analysis of numerical algorithms with subsequent re-writing. This in-depth analysis determined that at present achievable speeds are limited by the communication between processors (MPI). Even as the number of cores/domains can increase to several hundred thousand, due to communication overheads the wall clock time it takes to update a flowfield is bounded. We expect that as more users get access to hundreds of thousands of cores and the domain size per core starts shrinking, they will also encounter this 'minimum timestep barrier'.
机译:本文总结了去年FEFLO的主要改进和发展,FEFLO是基于自适应,非结构化网格的通用CFD代码。全面的模拟管道的各个方面:预处理,网格化,现场求解器和后处理均取得了重要进展,并得到了解决。具有数百万个内核的机器的出现将许多开发重点放在了场求解器和多物理场模块的分布式存储方面。多物理场的并行网格生成,粒子和流,并行插值,并行域分裂和重新划分都已考虑在内。此外,至强和AMD芯片的时间安排使人们认识到,与浮点运算相比,内存传输起着重要的作用,这是以前几代芯片所不具备的。这导致对数值算法进行了彻底的分析,并随后进行了重写。这项深入的分析确定,目前可达到的速度受到处理器(MPI)之间的通信的限制。即使核心/域的数量可以增加到数十万,由于通信开销,更新流场所需的挂钟时间也受到限制。我们期望随着越来越多的用户访问成千上万个内核,并且每个内核的域大小开始缩小,他们还将遇到这种“最小时间步长障碍”。

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