A 6th order continuous time band-pass Sigma Delta Analog to Digital modulator with active inductor based resonators

摘要

This paper presents a 6th order, continuous time bandpass Sigma Delta Analog to Digital modulator in IBM 0.18 um CMOS technology. In order to decrease chip area we replace traditional RLC circuits, containing low quality factor spiral inductors with high quality factor, active inductor based resonators utilizing negative impedance circuits. We see a reduction in chip area and post processing needs are eliminated. Pad to pad simulation of the extracted layout in Cadence yields an enhanced SNDR of 70 dB and a power consumption of 29 mW. An extra active inductor resonator is included on chip for characterization. Our modulator occupies 0.5 mm2 of chip area without pads.