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Cu Recrystallization and the Formation of Epitaxial and Non-Epitaxial Cu/Cu/Cu Interfaces in Stacked Blind Micro Via Structures

机译:Cu重结晶和形成堆叠盲微通结构中外延和非外延Cu / Cu / Cu / Cu / Cu / Cu / Cu / Cu界面的形成

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A key factor in achieving high electrical reliability in multilayer HDI PCBs is the integrity of the target pad - electroless Cu - electrolytic Cu interface (Cu/Cu/Cu-interface), especially in stacked blind micro via interconnections (BMVs). In the present paper it is shown, that aside from a low density of nanovoids, the formation of epitaxial Cu/Cu/Cu interfaces is important in satisfying the highest reliability requirements. Using example microstructures that are typical to stacked BMVs, the post-plating formation of epitaxial and non-epitaxial interfaces are described through the concept and mechanisms of “bottom-up” and “top-down” recrystallization. Epitaxial Cu/Cu/Cu interfaces typically form through unhindered “bottom-up” recrystallization across both interfaces and penetrate deep into the electrolytically deposited Cu layer (ECD Cu). The ability of thin electroless Cu layers (< 200 nm) to recrystallize in a “bottom-up” fashion is generally high. However, if there is an appreciable pre-existing contamination of the target pad surface, due to smear residues or a persistent organic layer etc, then such contaminants are determined to be critical factors as they can inhibit this “bottom-up” recrystallization across the target pad - electroless Cu interface. When this occurs, the electroless Cu layer is said to recrystalise in a “top-down” manner, as recrystallisation is determined to initiate on the ECD Cu side, and a non-epitaxial electroless Cu/ECD Cu interface results. Such occurrences can typically be avoided though the use of a horizontal “wet-to-wet” plating sequence, otherwise a more common observation is one of a non-epitaxial electroless Cu/ECD Cu interface. Additionally, it has been found that a high codeposition of the ECD-plating additives within the first $1 mumathrm{m}$ of plated ECD Cu, greatly reduces the ability for “bottom-up” recrystallization to occur, and typically gives rise to an alignment of grain boundaries in this region. Failure analysis carried out after reliability testing has shown that such alignment of grain boundaries can be causative for a premature crack formation, and based on these findings, a fatigue-like crack formation mechanism is proposed, and recommendations given to improve the epitaxy of Cu/Cu/Cu interconnections.
机译:在多层HDI PCB中实现高电性可靠性的关键因素是目标焊盘电解Cu - 电解Cu接口(Cu / Cu / Cu接口)的完整性,尤其是通过互连(BMV)堆叠盲微。在本文中,示出了,除了纳米膜的低密度之外,外延Cu / Cu / Cu接口的形成对于满足最高可靠性要求是重要的。使用典型的堆叠BMV的示例微结构,通过“自下而上”和“自上而下”再结晶的概念和机制描述外延和非外延接口的后电镀和非外延界面。外延Cu / Cu / Cu / Cu / Cu / Cu / Cu接口通常通过跨接口的无阻碍的“自下而上”重结晶形成,并深入地进入电解沉积的Cu层(ECD Cu)。薄的化学型Cu层(<200nm)以“自下而上”方式重结晶的能力通常很高。然而,如果由于涂片残留物或持续有机层等存在可明显的预先存在的靶垫表面污染,则这些污染物被确定为关键因素,因为它们可以抑制在整个上的“自下而上”重结晶目标垫 - 化学铜界面。当发生这种情况时,将电铜层置于“自上而下”方式重新结晶,因为确定在ECD Cu侧启动的重结晶,以及非外延化学型Cu / ECD Cu接口结果。通常可以避免这种发生,尽管使用水平的“湿到湿”电镀序列,否则更常见的观察是非外延电解Cu / ECD Cu接口之一。另外,已经发现,第一镀层添加剂的高分素 $ 1 mu mathrm { m} $ 电镀ECD Cu大大减少了“自下而上”重结晶的能力,并且通常引起该区域中的晶界的对准。在可靠性测试之后进行的失败分析表明,这种晶界的这种对准可能是造成过早裂缝形成的致病性,并且基于这些发现,提出了一种疲劳的裂缝形成机制,并提出了改善Cu /外延的建议。 CU / CU互连。

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