A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares

摘要

This paper presents a systematic design of tamper-resistant Galois-Field (GF) arithmetic circuits based on Threshold Implementation (TI) where a secret variable is represented with multiple variables, called shares, given by random numbers. TI is one of the countermeasures against Differential Power Analysis (DPA) on cryptographic hardware. The security order of TI depends on the number of shares. The minimum number of shares to be resistant dth-order DPA is said to be (d + 1). While the construction of GF arithmetic circuits of quadratic function based on TI with (d + 1) shares is known, it is not known how to construct other types of circuits based on it. In this paper, we present a generalization and systematic method of constructing the TI with (d + 1) input shares for any kind of GF arithmetic circuit in order to design a larger variety of tamper-resistant GF arithmetic circuits. We then apply the proposed method to a cryptographic hardware design in order to demonstrate its efficiency.