Integrated in a 0.35 μm 700 V BCD process platform, ultra-low Ron, sp 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which Ron, sp are 11.5 Ω·mm2 and 11.2 Ω·mm2, respectively. Utra-low Ron, sp benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.
展开▼
机译：本文提出了集成在0.35μm700 V BCD工艺平台中的超低Ron，sp 700 V自ISO（隔离）和NISO（非隔离）DB-nLDMOS（双P埋层nLDMOS）。 NISO和ISO DB-nLDMOS分别达到800 V和780 V，其中Ron，sp分别为11.5Ω·mm 2 和11.2Ω·mm 2 。超低Ron，sp得益于优化的器件尺寸以及对P型埋层植入后退火温度和时间的严格限制。对于ISO DB-nLDMOS，通过分别注入NWELL，可以在栅极多晶硅下获得低掺杂浓度的NWELL漂移区，从而避免了鸟嘴周围的雪崩击穿。此外，还展示了具有创新3D夹断结构的600 V DB-nJFET（双P埋层nJFET）。
展开▼
