Performance verification of a 12-Bit, 25Msps, successive approximation register analogue-to-digital converter on 65nm CMOS

摘要

This paper presents a system constructed to verify the performance of a 12-Bit, 25Msps SAR ADC fabricated on 65nm CMOS. The measurement methods and results are also presented. The system is based around a modular PXI (PCI eXtensions for Instrumentation) platform with software control developed in the labview? graphical programming environment. The precision capabilities and flexible configuration of the platform enables automated and reliable measurements of both static and dynamic ADC parameters and ensures that the errors measured are those of the ADC and not those of the measurement system. Measured ADC performance is in line with expectations under limited conditions. In addition to verifying static and dynamic ADC performance, the measurement system proved effective in evaluating the on-chip digital background calibration algorithm. With the addition of an FPGA module, the system has the potential to be further developed into an ADC calibration algorithm development and verification platform.