首页> 外文会议>International Conference on Field Programmable Logic and Applications >FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet
【24h】

FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet

机译:FLUENT10G:用于多10千兆以太网的基于可编程FPGA的网络测试仪

获取原文

摘要

We present FlueNT10G, an open-source FPGA-based network tester for precise replay of network traces, as well as for accurate packet capture and round-trip latency measurements. FlueNT10G streams replay and capture data between the host system and the FPGA board during active tests. It enables continuous measurements without being constrained by the memory capacity of the FPGA board. FlueNT10G is able to concurrently replay and capture traffic on three 10 Gbit/s network interfaces for all packet sizes. When operated exclusively in replay or capture mode, throughput increases to 4x 10 Gbit/s. Our design yields a temporal resolution of 6.4 ns for precise traffic pattern generation, as well as for accurate arrival timestamping and latency measurements. On the software-side, FlueNT10G is complemented by an API enabling the programmable execution of reproducible network measurements. Targeting the automated performance evaluation of different virtualized network function configurations, the API further integrates access to a bidirectional side-band channel for device-under-test reconfiguration and status feedback. FlueNT10G has been implemented on the NetFPGA-SUME platform (Xilinx Virtex-7 XC7VX690T) with an FPGA resource utilization of no more than 25%, which leaves sufficient capacity available for future design extensions.
机译:我们呈现FLUENT10G,一个基于开源FPGA的网络测试仪,用于精确重放网络迹线,以及准确的数据包捕获和往返延迟测量。 FLUENT10G流在主动测试期间在主机系统和FPGA板之间重放和捕获数据。它可以连续测量而不受FPGA板的存储器容量的约束。 Fluent10G能够同时重播和捕获所有数据包大小的三个10 Gbit / s网络接口上的流量。仅在重放或捕获模式下专门操作时,吞吐量增加到4倍10 Gbit / s。我们的设计为精确的交通模式生成产生6.4 ns的时间分辨率,以及准确到达时间戳和延迟测量。在软件侧,FLUENT10G由API补充,使可编程执行可再现的网络测量值。针对不同虚拟化网络功能配置的自动性能评估,API进一步集成了对双向边带通道的访问,以进行测试的重新配置和状态反馈。 FLUENT10G已在NetFPGA-Sume平台(Xilinx Virtex-7 XC7VX690T上)实现,FPGA资源利用率不超过25%,这留下了可用于未来设计扩展的足够容量。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号