Voltage mode implementation of highly accurate analog multiplier circuit

摘要

A new four-quadrant multiplier circuit is presented in this paper. Compared to the corresponding already published works, the accuracy of the circuit as well as the linearity performance is significantly improved. DC transfer characteristic of the circuit shows the nonlinearity error of 1.1% over a considerable range of the inputs. The performance of the circuit, in terms of the conceivable mismatch in trans-conductance parameter and threshold voltage are thoroughly analyzed. The circuit is simulated using HSPICE with TSMC level 49 (BSIM3v3) parameters for 0.18 μm CMOS technology, where under supply voltage of 1.8 V the -3 dB bandwidth of the proposed circuit is 1.45 GHz and the total harmonic distortion at 1 MHz, remains as low as 0.4 %.