Sub-ps Resolution Programmable Delays Implemented in a Xilinx FPGA

摘要

In this paper, a novel way to finely tune a net delay on Xilinx Field Programmable Gate arrays (FPGAs) is proposed. It consists of adding floating interconnects (nodes) to the net on which the delay is to be tuned, connected to any input pin of a switch matrix along the net. Adding nodes is made with a TCL script applied to an already placed and routed design. However, such nodes, also called antennas, typically cause fatal errors during the design flow and normally prevent the tools from generating the bit stream. To overcome this issue, a breadth-first search algorithm connecting each node to a load is proposed in this work. Experimental results conducted on a ZYNQxc7z010-3clg400 Xilinx FPGA using the Vivado Design suite showed that it is possible to add small delay steps to a net with a resolution under a pico-second and a covered range proportional to the number of added nodes reaching 48.6 ps for a net with 15 added nodes.