Hardware Implementation of the Baillie-PSW Primality Test

摘要

The need for large primes in major cryptographic algorithms has stirred interest in methods for prime generation. Recently, to improve confidence and security, prime number generation in hardware is being considered as an alternative to software. Due to time complexity and hardware implementation issues, probabilistic primality tests are generally preferred. The Baillie-PSW primality test is a strong probabilistic test; no known Baillie-PSW pseudoprime exists. In this paper, we discuss different types of cryptographic algorithms and primality tests, and review hardware implementations of the Miller-Rabin and Lucas tests. We also present the implementation of a Verilog-based design of the Baillie-PSW test on an Altera Cyclone IV GX FPGA. To our knowledge, this is the first hardware implementation of this test. The implementation takes an odd random number as input and returns the next immediate probable prime number as output. We analyze the results from our implementation and suggest methods to further improve our results in future.