We present a heuristic based approach towards analyzing and optimizing the throughput of asynchronous pipelined circuits. Optimization allows specification of the target throughput. A variety of handshaking protocols and implementations are supported through a library approach. Timing arcs specified for library cells serve as a basis for throughput analysis. The algorithms described in the paper are implemented and tested within the Weaver flow for a set of benchmarks synthesized using a simple library implementing PCHB protocol. Feasibility of the approach is demonstrated by the results for over 100 designs.
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