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Insert Save: Energy Optimization in IP Core Integration for FPGA-based Real-time Systems

机译:插入和保存:基于FPGA的IP核心集成中的能量优化

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Today, many industrial, automotive and autonomous systems like robots are deployed in high-temperature and battery-powered environments. Due to cooling and runtime, this limits the energy consumption and makes the design of such embedded real-time systems even more challenging. Though Field Programmable Gate Arrays (FPGAs) offer the required performance, their static and – load-dependent – dynamic energy consumptions continue to prevent a widespread adoption. The existing methods for dynamic power reduction (like clock gating) are either limited in savings or require disruptive changes to well-established FPGA design flows. Whilst the former is caused by optimizing on fabric level only, the latter is due to the lack of support for a more efficient (but not yet mature and standardized) high-level design entry in current tools. In this paper, we thus explore an optimization methodology based on an existing, but not-fully-utilized intermediate level of abstraction that emerges in the IP core integration phase of the design. To this end, we exploit the fact that the vast majority of FPGA-based real-time processing pipelines is not exclusively assembled using a single type of design entry – i.e., neither entirely hand-written nor high-level synthesis only. Instead, suitable IP cores (from a variety of sources) are integrated via standardized bus interfaces such as AXI, Avalon or Wishbone. To facilitate effort- and power-efficient clock gating on integration-level, we present two “insert and save” IP cores that harness application information extracted from current AXI3 and AXI4-Stream interfaces. Based thereon, both cores precisely control the clock signals of every downstream processing stage for maximum energy savings. This approach not only nicely integrates with today’s predominantly AXI-based designs but also results in clock gating structures that are particularly suitable for current FPGAs – as demonstrated by experimental evaluations on a Zynq-based Visual Servoing System with energy savings of 26%.
机译:如今,许多工业,汽车和自治系统,如机器人部署在高温和电池供电的环境中。由于冷却和运行时,这限制了能量消耗,使得这种嵌入式实时系统的设计更具挑战性。虽然现场可编程门阵列(FPGA)提供所需的性能,但它们的静态和加载依赖性 - 动态能量消耗继续,以防止广泛采用。现有的动态功率减少(如时钟门控)的方法是节省的限制,或者需要对良好的FPGA设计流程进行破坏性变化。虽然前者是通过仅在织物级别的优化引起的,但后者是由于缺乏对当前工具中更有效(但尚未成熟和标准化的)高级设计进入的支持。在本文中,我们基于现有但不完全利用的中间抽象探索优化方法,其在设计的IP核心集成阶段中出现。为此,我们利用了绝大多数基于FPGA的实时处理管道,不使用单一类型的设计进入 - 即,仅完全手写或高级合成。相反,合适的IP核心(来自各种源)通过标准化的总线接口集成,例如AXI,Avalon或Wishbone。为了便于在集成级别的努力和高功率的时钟门控,我们呈现了两个“插入和保存”IP核心,该IP核心从当前AXI3和AXI4流接口中提取的利用应用信息。基于其间,两个核心都精确地控制了每个下游处理阶段的时钟信号,以获得最大的节能。这种方法不仅与当今基于AXI的基于AXI的设计集成,而且还导致时钟门控结构特别适用于当前FPGA的结构 - 如通过基于Zynq的视觉伺服系统的实验评估所证明的,其节能为26%。

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