A 60 GHz tunable LNA in 32 nm double gate MOSFET for a wireless NoC architecture

摘要

The performance, tunability and efficiency of double gate MOSFET (DG-MOSFET) low noise amplifier (LNA) is investigated. We propose a novel two-stage common source cascode LNA and study its gain switching properties via back gate tuning in 32 nm DG-MOSFETs that leads to variable and reconfigurable device performances not found in comparable amplifiers built with conventional CMOS architectures without additional hardware. The peak gain changes by almost 9 dB from 6 dB to 14.9 dB for back gate biases of 0.3 V and 0.7 V respectively. The 3-dB bandwidth ranges from 60 – 75 GHz. The noise figure of the LNA varies from 6.8 dB at 0.7 V to 12 dB at 0.3 V. The maximum dissipated power is 12 mW for 1.2 V supply. The minimum 3rd order input intercept point is found to be − 5.1 dBm. These performance parameters are either comparable or better to some of the recent LNA designs in ∼ 60 GHz frequency at different technologies compared in this text. Finally, we briefly illustrate the application of this DG-MOSFET gain tuning LNA for a Wireless Network on Chip architecture.