A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-#x03BC;m CMOS technology

摘要

A 10Gb/s quarter-rate 4-tap decision feedback equalizer (DFE) using new analog sampling and soft-decision technique is proposed in this paper. To verify the DFE, a 10Gb/s simplified transceiver is realized in 0.18μm CMOS, which consists of a clock receiver and generator, a data-path with DFE, a 4 to 1 MUX, an output driver and a bias generator. The simulation shows that the transceiver has no output error when it receives 10Gb/s 800mVpp PRBS7 data which passes through a RLGC (resistance, inductance, conductance and capacitance) channel with 22dB attenuation at 5GHz. The output data has a total jitter p-p of 6.3ps and a vertical eye opening of 577mVpp. The active chip area of the whole transceiver is 0.65mm × 0.24mm, while the DFE occupies only 0.13mm × 0.18mm and draws 9.7mA from 1.8V supply.