Balancing test cost reduction vs. measurements accuracy at test time

摘要

Reducing test costs of analog and RF circuits is a complex challenge, for which intuitive solution is to reduce test time. However, such reduction usually leads to a degradation of measurement accuracy not easy to handle when no model is available to understand the impact of the reduction. This work presents a novel method to evaluate the impact of test time reduction on yield accuracy, using only measured values and easy-to-obtain uncertainty models. The results proposed by this method provide a balance between test time reduction and yield accuracy. The proposed method is applied on the evaluation of a SNR measurement and provides a representation of the impact of measurement time reduction on yield loss.