Study of Circuit Evolution to Repair Design Flaws in FPGA Edge Computing Chips

摘要

Field Programmable Logic Gate Array (FPGA) seems to be a semicustom circuit in the field of special application integrated circuits and use in edge computing. In this study, the chip-level reliability design of the system is carried out from the perspective of fault tolerance and fault self-repair. A real-time fault-tolerant self-repair system structure based on SRAM FPGA is proposed, and the design structure is verified on Xilinx Virtex-6 FPGA. It was found that the energy consumption of different modules in this study increased under the fault-tolerant self-repair design, and when the number of carry chains increased, the detection delay and reconstruction time also increased, which is in line with physical phenomena. However, it has been verified by the designer, it is found that the design time of the designer can be greatly reduced by about 50%, which is an important contribution.