Generation of floating point 2D scaling operators for FPGA

摘要

This paper presents several architectures for an FPGA implementation of a matrix operator for geometric two dimensional scaling using floating point numbers. We have generated synthesizable VHDL implementations of the proposed architectures for several floating point precisions: half, simple and double. Besides the precision of the floating point operators, the parallelization degree of the internal processing units and the targeted overall frequency can be configured for the generator. Using a generator was also helpful for generating lots of unit tests for the generated operators, thus being able to easily validate the operators. Additionally, creating all the unit tests from the beginning of the development process, allowed to use a test driven approach for creating the code generator.