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7.1 A 1/4-inch 8Mpixel CMOS image sensor with 3D backside-illuminated 1.12#x03BC;m pixel with front-side deep-trench isolation and vertical transfer gate

机译:7.1 A 1/4英寸8mpixel CMOS图像传感器,带有3D背面照射的1.12μm像素,具有前侧深沟隔离和垂直传输门

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According to the trend towards high-resolution CMOS image sensors, pixel sizes are continuously shrinking, towards and below 1.0μm, and sizes are now reaching a technological limit to meet required SNR performance [1-2]. SNR at low-light conditions, which is a key performance metric, is determined by the sensitivity and crosstalk in pixels. To improve sensitivity, pixel technology has migrated from frontside illumination (FSI) to backside illumiation (BSI) as pixel size shrinks down. In BSI technology, it is very difficult to further increase the sensitivity in a pixel of near-1.0μm size because there are no structural obstacles for incident light from micro-lens to photodiode. Therefore the only way to improve low-light SNR is to reduce crosstalk, which makes the non-diagonal elements of the color-correction matrix (CCM) close to zero and thus reduces color noise [3]. The best way to improve crosstalk is to introduce a complete physical isolation between neighboring pixels, e.g., using deep-trench isolation (DTI). So far, a few attempts using DTI have been made to suppress silicon crosstalk. A backside DTI in as small as 1.12μm-pixel, which is formed in the BSI process, is reported in [4], but it is just an intermediate step in the DTI-related technology because it cannot completely prevent silicon crosstalk, especially for long wavelengths of light. On the other hand, front-side DTIs for FSI pixels [5] and BSI pixels [6] are reported. In [5], however, DTI is present not only along the periphery of each pixel, but also invades into the pixel so that it is inefficient in terms of gathering incident light and providing sufficient amount of photodiode area. In [6], the pixel size is as large as 2.0μm and it is hard to scale down with this technology for near 1.0μm pitch because DTI width imposes a critical limit on the sufficient amount of photodiode area for full-well capacity. Thus, a new technological advance is necessary to- realize the ideal front DTI in a small size pixel near 1.0μm.
机译:据向高分辨率的CMOS图像传感器的趋势,像素尺寸连续缩小,朝向和下面为1.0μm,现在大小达到技术限制,以满足所需的SNR性能[1-2]。 SNR在低光照条件下,这是一个关键的性能指标,是通过以像素为单位的灵敏度和串扰确定。为了提高灵敏度,像素技术已经从正面照明(FSI)到背面illumiation(BSI)像素作为尺寸缩小向下迁移。在BSI技术,它是非常困难的,以进一步提高在近1.0微米大小的像素的灵敏度,因为有用于从微透镜至光电二极管入射的光没有结构的障碍。因此,以改善低光SNR的唯一方法是减少串扰,这使得色彩校正矩阵(CCM)接近零的非对角元素,从而降低色彩噪声[3]。以改善串扰的最好方法是引入相邻像素之间,例如一个完整的物理隔离,使用深沟槽隔离(DTI)。到目前为止,使用DTI一些已经尝试打压硅串扰。背侧DTI在小至1.12μm像素,其在BSI工艺形成,在报道[4],但它是在DTI相关技术只是一个中间步骤,因为它不能完全地防止硅串扰,尤其是对光的长波长。在另一方面,前侧为DTIS FSI像素[5]和BSI像素[6]中报告。 [5]然而,DTI不仅沿着各像素的周边存在的,但也侵入到像素,以便它是在收集入射光并提供光电二极管区域的足够量方面效率低下。在[6]中,像素大小是一样大2.0微米,这是很难按比例缩小与此技术用于近1.0μm的间距,因为DTI宽度强加用于全阱容量的足够量的光电二极管面积的临界极限。于是,一种新的技术进步是必要的措施─实现理想前DTI在附近1.0μm的小尺寸的像素。

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